1. Field of Invention
The present invention relates generally to a method and apparatus for dry etching semiconductor wafers. More specifically, the invention relates to a method and concomitant apparatus for anisotropically etching a dielectric layer followed by in situ isotropic etching of a polysilicon layer.
2. Background of Invention
Trenches formed in semiconductor substrates have many uses in producing integrated circuits including isolation, capacitor formation, transistor formation, and so forth. One important use of trenches is in the formation of a trench capacitor as a storage node for a dynamic random access memory (DRAM) device. Trench capacitors are desirable because they occupy a relatively small area, while having large electrode surface area due to the depth of the trench used to form the capacitor.
FIGS. 1A through 1G collectively depict a portion of a conventional process of manufacturing the DRAM structure. In a first process chamber, a trench 12 is etched into a substrate 14 (FIG. 1A). The trench 12 is then lined with a first oxide 16 to condition the substrate 14 against dopant migration (FIG. 1B). The first oxide 16 is removed and a dielectric layer 18 is deposited (FIG. 1C). The trench 12 is filled and partially etched back with a first layer of polysilicon 20 (FIG. 1D). A second oxide 22 is deposited covering the first polysilicon layer 20 (FIG. 1E). The second oxide 22 is anisotropically etched in a second chamber to expose the underlying first layer of polysilicon 20 (FIG. 1F). A second layer of polysilicon 24 is deposited above the first layer of polysilicon 20 to fill the trench 12 (FIG. 1G).
Although the foregoing process yields a structure that is effectively used in a DRAM device, the number of process steps, and the number of chambers (both etch and deposition) required to produce the desired structure in the film stack is large. With such a large number of steps, and associated chambers required to execute those steps, the risk of device damage and contamination is correspondingly large as well. Additionally, the large number of steps places a burden on system throughput. For example, in order to anisotropically etch the second oxide to expose the underlying polysilicon, a parallel plate plasma reactor with capacitive coupling is generally used. Since prior art reactors are typically not capable of the selectivity needed to etch the underlying polysilicon without damaging nitride and oxide layers exposed in the film stack, a separate tool is typically used for the polysilicon etching step that follows in some specific process sequences. Etching the underlying polysilicon is performed in an etch reactor with isotropic etch capability. The need for switching chambers to etch the underlying polysilicon after the oxide etch increases the risk of damage to the film stack by exposing the wafer to additional environments and excessive handling.
Therefore, there is a need in the art for a method that clears a high aspect ratio trench, lined with a dielectric, having an anisotropic dielectric etch and an isotropic polysilicon etch sequentially performed in the same process chamber.